1. Field of the Invention
The present invention relates to a multi-layer circuit board for mounting an electronic part such as a semiconductor chip or a semiconductor device having a number of electrodes, pads, or lands, hereinafter referred to as lands, arranged in a lattice form or in a staggered form.
2. Description of the Related Art
In modem semiconductor devices, the logic devices are becoming highly functional and highly integrated, feature more inputs and outputs, and are being mounted ever more densely. Therefore, products have been produced to compensate for a lack of space for forming lands, and to cope with increased numbers of inputs and outputs, by arranging lands like an array on the land-forming surface of a semiconductor chip. FIG. 25 illustrates a prior art or mounting a semiconductor chip 4 on a substrate 5 relying on a flip chip connection. The semiconductor chip 4 shown here has lands 6 arranged on the outer peripheral edges thereof. Circuit patterns 7 are connected to the, lands 6 and are drawn outwardly. In this case the respective circuit patterns 7 are connected to the respective electrodes 6 on a single, common surface.
FIG. 24 illustrates the arrangement of lands on a wiring member for mounting a semiconductor chip having two rows of lands 6 arranged along the outer peripheral edges of the land-forming surface, and the arrangement of circuit patterns 7 connected to the lands 8. In this example, the pattern 7 is drawn from an intermediate portion of the space between the adjacent two lands 8; i.e., the respective circuit pattern 7 is drawn from the respective land 8 on a single common surface. In drawing the circuit patterns 7 from the lands 8 arranged in plural rows, it is general practice to connect a pattern on the land 8 of the inner side and to draw the pattern outwardly through the intermediate portion between the two adjacent lands 8 of the outer side.
When a number of lands are arranged like an array on the land-forming surface to increase the numbers of inputs and outputs, however, it becomes no longer possible to draw the wirings toward the outer side from all lands on the surface though it may vary depending upon the distance between the lands and the number of the lands.
To solve this problem, it has been contrived to form circuit boards in many layers for mounting a semiconductor chip, and to suitably arrange the circuit patterns on the laminated circuit boards, in order to electrically connect the lands to every land of the semiconductor chip and to make the circuit patterns. FIG. 26 illustrates an example where a semiconductor chip 4 is mounted on a multi-layer circuit board obtained by laminating a plurality of layers. Thus, according to the method of laminating the plurality of layers, it becomes possible to electrically connect the semiconductor chip 4 having a number of lands 6 arranged like an array to the external connection terminals without causing the circuit patterns to interfere. In FIG. 26, reference numeral 7a denotes a circuit pattern of an inner layer, and 5a to 5d denote circuit boards which are the first to fourth layers.
When the semiconductor chip having lands arranged like an array is to be mounted on the circuit board, about two circuit boards may be laminated one upon the other provided the number of the lands is not very large. When the semiconductor chip has as many pins as, for example, 30.times.30 pins or 40.times.40 pins, however, the circuit boards must be laminated in 6 to 10 layers.
When the circuit boards in which the circuit patterns are very densely formed are to be laminated in many layers, there will be employed a high-density wiring method such as build-up method accompanied, however, by serious problems in regard to yield of the products, reliability and the cost of production. That is, when the circuit patterns are to be formed in many layers, vias are formed in each layer to accomplish an electric connection between the circuit patterns and the circuit patterns across the layer, and the layers are successively laminated, requiring a high degree of precision without, however, offering high degree of reliability. When many layers are laminated, furthermore, it is required that none of the layers is defective, involving further increased technical difficulty.
To produce a multi-layer circuit board by laminating circuit patterns in many layers, while maintaining a good yield, a reduction in the number of wiring layers could be an effective solution.